The present invention relates generally to the manufacture of bipolar transistors and, more specifically, to the testing of developmental bipolar transistors under controlled stress conditions to provide qualification for commercial use.
Transistors are used as either amplifying or switching devices in electronic circuits. In the first application, the transistor functions to amplify small ac signals. In the second application, a small current is used to switch the transistor between an xe2x80x9conxe2x80x9d state and an xe2x80x9coffxe2x80x9d state.
An xe2x80x9cFETxe2x80x9d is a field effect transistor. There are two major types of FET""s, the metal-oxide-semiconductor field effect transistor or MOSFET (also called an insulated-gate FET, or IGFET), and the junction-gate FET, or JFET. An FET has a control gate, and source and drain regions formed in a substrate. The control gate is formed above a dielectric insulator that is deposited over the area between the source and drain regions. As voltage is applied to the control gate, mobile charged particles in the substrate form a conduction channel in the region between the source and drain regions. Once the channel forms, the transistor turns xe2x80x9conxe2x80x9d and current may flow between the source and drain regions.
The bipolar transistor is an electronic device with two p-n junctions in close proximity. The bipolar transistor has three device regions: an emitter, a collector, and base disposed between the emitter and the collector. Ideally, the two p-n junctions (the emitter-base and collector-base junctions) are in a single layer of semiconductor material separated by a specific distance. Modulation of the current flow in one p-n junction by changing the bias of the nearby junction is called xe2x80x9cbipolar-transistor action.xe2x80x9d
External leads can be attached to each of the three regions and external voltages and currents can be applied to the device using these leads. If the emitter and collector are doped n-type and the base is doped p-type, the device is an xe2x80x9cnpnxe2x80x9d transistor. Alternatively, if the opposite doping configuration is used, the device is a xe2x80x9cpnpxe2x80x9d transistor. Because the mobility of minority carriers (i.e., electrons) in the base region of npn transistors is higher than that of holes in the base of pnp transistors, higher-frequency operation and higher-speed performances can be obtained with npn devices. Therefore, npn transistors comprise the majority of bipolar transistors used to build integrated circuits.
In the manufacture of bipolar transistors, especially in the development of new bipolar transistor technology such as SiGe bipolar transistors, it is often necessary to put various populations of bipolar transistors under controlled stress conditions to qualify the transistors for commercial use. Presently, such transistors are stressed by exposing them to stress conditions that provide an approximation of constant current, constant voltage conditions for a predetermined time at a stress temperature. The stress conditions are determined for each application, but include parameters such as stress current, stress voltage, stress temperature, and stress duration. The stress temperature is typically provided by putting the transistor under stress in a stress oven.
A typical stress driver circuit 400 is shown in FIG. 1. Stress conditions are applied by increasing the voltage 11 until the desired emitter current is reached. The transistor bias is provided by resistors 410 and 420. The emitter current is determined by measuring the voltage drop across resistor 22. A plurality of such circuits connected to a single voltage source for stressing a plurality of transistors are typically provided. Because the stress conditions depend on the characteristics of the transistor 18 under stress, the stress conditions will change as the characteristics of the transistor 18 change under stress. Also, each of the plurality of transistors will be under somewhat different stress conditions because each transistor typically has somewhat different characteristics.
Typically, after exposing the plurality of transistors to the predetermined stress conditions for a predetermined time, the stress conditions are removed, and the transistors are physically moved from the stress oven to a parametric tester for characterization. This characterization is done to measure any degradation of the transistor device parameters over the course of the stress testing. The transistors are then returned to the stress oven, and the procedure is repeated until the transistors have received the total predetermined amount of stress.
The standard testing method does not include xe2x80x9cin situxe2x80x9d data collection while the transistors are under stress. There is some concern among those skilled in the art that characterizing a transistor after the stress conditions have been removed (and after the transistor has been physically handled) may provide some relaxation of the response of the transistor to stress. Therefore, the characterization performed after the stress has been interrupted may not portray a true picture of the response of the transistor to stress.
Furthermore, the standard stress driver circuit 400 does not provide for disconnection of the transistor upon failure. This shortcoming may cause the transistor to draw excessive current, which in turn may cause two problems. First, the excessive current draw from voltage source 11 in FIG. 1 may affect the stress conditions of the other transistors in the plurality of test circuits, especially if a number of them begin to fail. Second, the failing transistor may draw enough current that it causes an excessive amount of physical damage to itself. This damage would render the part useless to post-stress physical failure analysis. The analysis of a transistor that has xe2x80x9cburned outxe2x80x9d does not provide useful information as to the mechanism of the failure. Accordingly, the standard method fails to provide a full understanding of the failure modes of the transistors that fail under stress.
Constant current source circuits, such as circuit 10 shown in FIG. 2, are well known in the art for providing a source of constant current I from a voltage source 11 to a load 12. The circuit comprises an operational amplifier or xe2x80x9cop ampxe2x80x9d 14, with voltage input or Vin 30, a field effect transistor (FET) 16, bipolar transistor 18 and a resistor 20 connected to an emitter node 24, and a precision resistor 22 of resistance R. A node 25 is connected to the drain of FET 16 and to the collector of transistor 18. Circuit 10 provides a constant current of I=Vin/R to load 12.
When the positive (+, or non-inverting) input of an op amp is higher (in voltage) than the negative (xe2x88x92, or inverting) input, the voltage at the output goes up. Conversely, when the negative input is higher than the positive input, the output goes down. It can be seen in FIG. 2 that op amp 14 is connected in a negative feedback configuration. FET 16 and resistor 20 provide the base bias to transistor 18. When the output of op amp 14 increases, the base bias increases, causing transistor 18 to conduct more, increasing its current flow, thereby increasing the emitter voltage (at resistor 22). This increases the voltage at the negative input of op amp 14, causing its output to decrease. This negative feedback configuration causes op amp 14 to maintain the voltage at the emitter of transistor 18 equal to Vin. When in a negative feedback configuration, the output of an op amp will go to whatever voltage is necessary to maintain its inputs at equal voltages, as is well-known in the art.
Because the voltage at resistor 22, having a resistance R, is maintained at Vin, the current through resistor 22 is I=Vin/R. For all practical purposes, there is negligible current flow into op amp 14, and into the gate of FET 16. Therefore, the current in resistor 22 is equal to the current in the load 12. Because resistor 22 is of a precision resistance, and Vin is set by an accurate voltage source, the load current can be set and maintained with precision.
Although circuit 10 is known in the art for providing a constant current to load 12, such a circuit is not ideal for use in stressing the bipolar transistor 18. Specifically, op amp 14 is intended to control the current through resistor 22, which is not the same as the emitter current. These currents differ by the current flowing through FET 16 and resistor 20. This differential current represents an error factor that will be different for each of the transistors being stressed, and that will change in magnitude over the course of the stress testing.
The present invention proposes an improved testing system and methodology that not only provide a true constant current to the transistor device under test, but also provide for constant voltage (Vce), constant temperature, in situ data collection, and automatic device disconnect upon failure. The improved testing system and methodology further eliminate the need for physically handling the devices before the stress testing is complete. Thus, the improved testing system and methodology address needs that are not addressed by stress driver circuitry known in the art.
The present invention provides a stress-driver circuit for delivering a constant voltage (Vce) and a constant current (I=Vin/R) to a bipolar transistor under stress. The circuit comprises a power source, an op-amp, a FET, the bipolar transistor, and first and second resistors. The power source is connected to the bipolar transistor collector and the drain of the FET. The op-amp has a positive input biased at an input voltage (Vin) and a negative input having a feedback loop connected the negative input. The feedback loop is connected to the bipolar transistor emitter. The op-amp output is connected to the FET gate. The FET drain is connected to the power supply, and the FET source is biased to ground through a first resistor and connected to the base of the bipolar transistor. The second resistor has a resistance R and is connected at one end to the bipolar transistor emitter and biased to ground at the other end.
An automatic trip circuit may be provided between the power source and a node to which the FET drain and the transistor device collector are connected. The automatic trip circuit is adapted to cut off power to the bipolar transistor and FET if the collector current of the bipolar transistor exceeds a predetermined limit. The automatic trip circuit may comprise logic that is optically isolated from the power supply current.
One or more parameter readout circuits each for providing a readout of current, voltage, or a combination of current and voltage may be provided in predetermined areas of the stress-driver circuit. The parameter readout circuits may be located, for example, to provide a readout of current to the bipolar transistor collector, current from the bipolar transistor emitter, current to the bipolar transistor base, voltage across the bipolar transistor collector and emitter, or a combination of these parameters. Each parameter readout circuit may comprises a precision resistor, an instrumentation amplifier, or a combination of these devices.
The automatic trip circuit may comprise a comparitor having a positive input connected to the reference voltage, a negative input connected to the collector current sense point, and an output; an optoisolator; a reset connected to the optoisolator; and a photovoltaic relay switch connected to the optoisolator, the power supply, and the bipolar transistor collector. The automatic trip circuit is adapted to function such that activation of the reset latches the optoisolator on, closing the photovoltaic relay switch to allow current to flow from the power supply to the bipolar transistor collector until the transistor collector current exceeds the predetermined limit and drives the comparitor low. This turns off the light emission from the LED in the optoisolator, causing power to be cut to the LED in the photovoltaic relay. This opens the photovoltaic relay switch and cuts off current flow from the power supply to the bipolar transistor collector. The reset may comprise a power-on-reset with clamp. Such an automatic trip circuit may be adapted to cut off power from a power supply to any predetermined device if a measured current exceeds a predetermined limit.
The invention also comprises a method for testing a bipolar transistor with the stress-driver circuit described above. The method comprises installing the bipolar transistor in the stress-driver circuit; supplying a constant voltage (Vce) and constant current (I=Vin/R) to the transistor within the stress-driver circuit for a predetermined amount of time while exposing the transistor to a stress temperature; and evaluating the impact of current, voltage, time, and temperature on the transistor device. The method may further comprise an automatic trip circuit cutting off power to the bipolar transistor and the FET if a measured current of the bipolar transistor collector exceeds a predetermined limit. The method may still further comprise monitoring current, voltage, or a combination of current and voltage in one or more predetermined areas of the stress-driver circuit during the test using one or more parameter readout circuits.
It is to be understood that both the foregoing general description and the following detailed description are exemplary, but are not restrictive, of the invention.